library ieee;
use ieee.std_logic_11.all;
generic(k : positive := 3); --input number word length less one
port( multiplicand : in bit_vector(k downto 0);
multiplier : in bit_vector(k downto 0);
clock : in bit;
product : inout bit_vector((2*k + 2) downto 0);
final : out bit
);
end booth_multiplier;
architecture structural of booth_multiplier is
signal mdreg : bit_vector(k downto 0);
signal adderout : bit_vector(k downto 0);
signal carries : bit_vector(k downto 0);
signal augend : bit_vector(k downto 0);
signal tcbuffout : bit_vector(k downto 0);
signal adder_ovfl : bit;
signal comp : bit;
signal clr_md : bit;
signal load_md : bit;
signal clr_pp : bit;
signal load_pp : bit;
signal shift_pp : bit;
signal boostate : natural range 0 to 2*(k + 1) :=0;
begin
process --main clocked process containing all sequential elements
begin
wait until (clock'event and clock = '1'); --register to hold multiplication
multiplicand during
if clr_md = '1' then
mdreg <= (others => '0');
elsif load_md = '1' then
mdreg <= multiplicand;
else
mdreg <= mdreg;
end if;
--register/shifter accumulates partial product values
if clr_pp = '1' then
product <= (others => '0');product((k+1) downto 1) <= multiplier;
elsif load_pp = '1' then
product((2*k + 2) downto (k + 2)) <= adderout; --add to top half
product((k+1) downto 0) <= product((k+1) downto 0); --refresh bootm half
elsif shift_pp = '1' then
product <= product sra 1; --shift right with sign extend
else
product <= product;
end if;
end process;
--adder adds/subtracts partial product to multiplicand
augend <= product((2*k+2) downto (k+2));
addgen : for i in adderout'range
generate
lsadder : if i = 0 generate
adderout(i) <= tcbuffout(i) xor augend(i) xor product(1);
carries(i) <= (tcbuffout(i) and augend(i)) or
(tcbuffout(i) and product(1)) or
(product(1) and augend(i));
end generate;
otheradder : if i /= 0 generate
adderout(i) <= tcbuffout(i) xor augend(i) xor carries(i-1);
carries(i) <= (tcbuffout(i) and augend(i)) or
(tcbuffout(i) and carries(i-1)) or
(carries(i-1) and augend(i));
end generate;
end generate;
--twos comp overflow bit
adder_ovfl <= carries(k-1) xor carries(k);
--true/complement buffer to generate two's comp of mdreg
tcbuffout <= not mdreg when (product(1)='1') else mdreg;
--booth multiplier state counter
process begin
wait until (clock'event and clock = '1');
if boostate < 2*(k + 1) then
boostate <= boostate + 1; final <='0';
else
final <='1';boostate <= 0;
end if;
end process;
--assign control signal values based on state
process(boostate)
begin
--assign defaults, all registers refresh
clr_md <= '0';
load_md <= '0';
clr_pp <= '0';
load_pp <= '0';
shift_pp <= '0';
--boostate <=0;
if boostate = 0 then
load_md <= '1';clr_pp <= '1';
elsif boostate mod 2 = 0 then --boostate = 2,4,6,8 ....
shift_pp <= '1';
else --boostate = 1,3,5,7......
if product(1) = product(0) then
null; --refresh pp
else
load_pp <= '1'; --update product
end if;
end if;
end process;
end structural;
