8255a[1]

DescriptionTheHarris82C55AisahighperformanceCMOSversionoftheindustrystandard8255Aandismanufacturedusingaself-alignedsilicongateCMOSprocess(ScaledSAJIIV).ItisageneralpurposeprogrammableI/Odevicewhichmaybeusedwithmanydifferentmicroprocessors.Thereare24I/Opinswhichmaybeindividuallyprogrammedin2groupsof12andusedin3majormodesofoperation.Thehighperformanceandindustrystandardconfigurationofthe82C55Amakeitcompatiblewiththe80C86,80C88andother microprocessors.StaticCMOScircuitdesigninsureslowoperatingpower.TTLcompatibilityoverthefullmilitarytemperaturerangeandbusholdcircuitryeliminatetheneedforpull-upresistors.TheHarrisadvancedSAJIprocessresultsinperformanceequaltoorgreaterthanexistingfunctionallyequivalentproductsata fraction of the power.June 1998

Features•Pin Compatible with NMOS 8255A•24 Programmable I/O Pins•Fully TTL Compatible•HighSpeed,No“WaitState”Operationwith5MHzand8MHz 80C86 and 80C88•Direct Bit Set/Reset Capability•Enhanced Control Word Read Capability•L7 Process•2.5mA Drive Capability on All I/O Ports•Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µAOrdering InformationPART NUMBERS5MHz8MHzCP82C55A-5IP82C55A-5CS82C55A-5IS82C55A-5CD82C55A-5ID82C55A-58406601QACP82C55AIP82C55ACS82C55AIS82C55ACD82C55AID82C55A8406602QATEMPERATUREPACKAGERANGE40 Ld PDIP44 Ld PLCC40 LdCERDIPSMD#44 PadCLCCSMD#-55oC to 125oC0oC to 70oC-40oC to 85oC0oC to 70oC-40oC to 85oC0oC to 70oC-40oC to 85oC-55oC to 125oCPKG.NO.E40.6E40.6N44.65N44.65F40.6F40.6F40.6F40.6J44.AJ44.AMD82C55A-5/BMD82C55A/BMR82C55A-5/BMR82C55A/B8406601XA8406602XAPinouts82C55A (DIP)TOP VIEWPA0PA3PA2PA1PA0RDCSGNDA1A0PC7PC6PC5PC4PC0PC1PC2PC3PB0PB1PB2123456710111213141516171819204039383736353433323130292827262524232221RDCS82C55A (CLCC)TOP VIEWPA1PA2PA3PA4PA5PA6PA7PA46543214443424140PA5PA6GND7PA7NC8WRA19RESETA010D0PC711D1PC612D2PC513D3PC414D4PC015D5PC116D6PC217D71819202122232425262728VCCPB7PB6PB5PB4PB3PC3PB0PB1PB2WR82C55A (PLCC)TOP VIEWRDPA0PA1PA2PA3NCPA4PA5PA6PA7WR39NC38RESET37D036D135D234D333D432D531D630D729NC6543214443424140CSGNDA1A0PC7NCPC6PC5PC4PC0PC1710111213141516171819202122232425262728PC2PC3PB0PB1PB2NCPB3PB4PB5PB6PB73938373635343332313029RESETD0D1D2D3NCD4D5D6D7VCCPB3PB4PB5PB6PB7VCCNCCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.Copyright © Harris Corporation 1998

File Number

2969.2

1

82C55APin DescriptionSYMBOLVCCGNDD0-D7RESETCSRDWRA0-A1PINNUMBER26727-343565368, 9I/OIIIIITYPEDESCRIPTIONVCC:The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 isrecommended for decoupling.GROUNDDATA BUS:The Data Bus lines are bidirectional three-state pins connected to thesystem data bus.RESET:Ahighonthisinputclearsthecontrolregisterandallports(A,B,C)aresetto the input mode with the “Bus Hold” circuitry turned on.CHIPSELECT:Chipselectisanactivelowinputusedtoenablethe82C55AontotheData Bus for CPU communications.READ:Read is an active low input control signal used by the CPU to read statusinformation or data via the data bus.WRITE:Write is an active low input control signal used by the CPU to load controlwords and data into the 82C55A.ADDRESS:These input signals, in conjunction with theRD andWR inputs, controlthe selection of one of the three ports or the control word register. A0 and A1 arenormally connected to the least significant bits of the Address Bus A0, A1.PORTA:8-bitinputandoutputport.Bothbusholdhighandbusholdlowcircuitryarepresent on this port.PORT B:8-bit input and output port. Bus hold high circuitry is present on this port.PORT C:8-bit input and output port. Bus hold circuitry is present on this port.PA0-PA7PB0-PB7PC0-PC71-4, 37-4018-2510-17I/OI/OI/OFunctional DiagramPOWERSUPPLIES+5VGNDGROUP ACONTROLGROUP APORT A(8)I/OPA7-PA0BI-DIRECTIONALDATA BUSD7-D0DATA BUSBUFFER8-BITINTERNALDATA BUSGROUP APORT CUPPER(4)GROUP BPORT CLOWER(4)I/OPC7-PC4I/OPC3-PC0RDWRA1A0RESETREADWRITECONTROLLOGICGROUP BCONTROLGROUP BPORT B(8)I/OPB7-PB0CS2

82C55AFunctional DescriptionData Bus BufferThisthree-statebi-directional8-bitbufferisusedtointerfacethe82C55Atothesystemdatabus.DataistransmittedorreceivedbythebufferuponexecutionofinputoroutputinstructionsbytheCPU.Controlwordsandstatusinforma-tion are also transferred through the data bus buffer.Read/Write and Control LogicThefunctionofthisblockistomanagealloftheinternalandexternaltransfersofbothDataandControlorStatuswords.ItacceptsinputsfromtheCPUAddressandControlbussesandinturn,issuescommandstobothoftheControlGroups.(CS)ChipSelect.A“low”onthisinputpinenablesthecommuncation between the 82C55A and the CPU.(RD)Read.A“low”onthisinputpinenables82C55AtosendthedataorstatusinformationtotheCPUonthedatabus.Inessence, it allows the CPU to “read from” the 82C55A.(WR)Write.A“low”onthisinputpinenablestheCPUtowrite data or control words into the 82C55A.(A0andA1)PortSelect0andPortSelect1.Theseinputsignals,inconjunctionwiththeRDandWRinputs,controltheselectionofoneofthethreeportsorthecontrolwordregister.Theyarenormallyconnectedtotheleastsignificantbits of the address bus (A0 and A1).82C55A BASIC OPERATIONINPUT OPERATION(READ)Port A→Data BusPort B→Data BusPort C→Data BusControl Word→Data BusOUTPUT OPERATION(WRITE)00110101111100000000Data Bus→Port AData Bus→Port BData Bus→Port CData Bus→ControlDISABLE FUNCTIONXXXXX1X110Data Bus→Three-StateData Bus→Three-StatePOWERSUPPLIES+5VGNDGROUP ACONTROLGROUP APORT A(8)I/OPA7-PA0BI-DIRECTIONALDATA BUSDATABUSD7-D0BUFFERGROUP APORT CUPPER(4)8-BITINTERNALDATA BUSGROUP BPORT CLOWER(4)I/OPC7-PC4I/OPC3-PC0RDWRA1A0RESETREADWRITECONTROLLOGICGROUP BCONTROLGROUP BPORT B(8)I/OPB7-PB0CSFIGURE1.82C55ABLOCKDIAGRAM.DATABUSBUFFER,READ/WRITE, GROUP A & B CONTROL LOGICFUNCTIONS(RESET)Reset.A“high”onthisinputinitializesthecontrolregisterto9Bhandallports(A,B,C)aresettotheinputmode.“Bushold”devicesinternaltothe82C55AwillholdtheI/Oportinputstoalogic“1”statewithamaximumholdcurrent of 400µA.Group A and Group B ControlsThefunctionalconfigurationofeachportisprogrammedbythesystemssoftware.Inessence,theCPU“outputs”acon-trolwordtothe82C55A.Thecontrolwordcontainsinformationsuchas“mode”,“bitset”,“bitreset”,etc.,thatini-tializes the functional configuration of the 82C55A.EachoftheControlblocks(GroupAandGroupB)accepts“commands”fromtheRead/WriteControllogic,receives“controlwords”fromtheinternaldatabusandissuestheproper commands to its associated ports.Control Group A - Port A and Port C upper (C7 - C4)Control Group B - Port B and Port C lower (C3 - C0)Thecontrolwordregistercanbebothwrittenandreadasshowninthe“BasicOperation”table.Figure4showsthecontrolwordformatforbothReadandWriteoperations.Whenthecontrolwordisread,bitD7willalwaysbealogic“1”, as this implies control word mode information.A10011A00101RD0000WR1111CS00003

82C55APorts A, B, and CThe82C55Acontainsthree8-bitports(A,B,andC).Allcanbeconfiguredtoawidevarietyoffunctionalcharacteristicsbythesystemsoftwarebuteachhasitsownspecialfeaturesor“personality”tofurtherenhancethepowerandflexibilityofthe 82C55A.PortAOne8-bitdataoutputlatch/bufferandone8-bitdatainputlatch.Both“pull-up”and“pull-down”bus-holddevicesare present on Port A. See Figure 2A.PortBOne8-bitdatainput/outputlatch/bufferandone8-bitdata input buffer. See Figure 2B.PortCOne8-bitdataoutputlatch/bufferandone8-bitdatainputbuffer(nolatchforinput).Thisportcanbedividedintotwo4-bitportsunderthemodecontrol.Each4-bitportcon-tainsa4-bitlatchanditcanbeusedforthecontrolsignaloutputandstatussignalinputsinconjunctionwithportsAand B. See Figure 2B.MASTERRESETOR MODECHANGEINTERNALDATA ININTERNALDATA OUT(LATCHED)OUTPUT MODEINPUT MODEMODE 1RD,WRD7-D082C55AMODE 0B8I/O4CA0-A1CSA4I/O8I/Oregisterwillcontain9Bh.Duringtheexecutionofthesystemprogram,anyoftheothermodesmaybeselectedusingasingleoutputinstruction.Thisallowsasingle82C55Atoserviceavarietyofperipheraldeviceswithasimplesoftwaremaintenanceroutine.Anyportprogrammedasanoutputportisinitializedtoallzeroswhenthecontrolwordiswritten.ADDRESS BUSCONTROL BUSDATA BUSI/OPB7-PB0B8I/OPC3-PC0CPC7-PC4PA7-PA0A8I/OEXTERNALPORT A PINPB7-PB0MODE 2CONTROLCONTROLOR I/OOR I/OCPA7-PA0B8I/OABI-DIRECTIONALFIGURE 2A.PORT A BUS-HOLD CONFIGURATIONRESETOR MODECHANGEVCCPPB7-PB0CONTROLPA7-PA0FIGURE 3.BASIC MODE DEFINITIONS AND BUS INTERFACECONTROL WORDINTERNALDATA ININTERNALDATA OUT(LATCHED)OUTPUT MODEEXTERNALPORT B, CPIND7D6D5D4D3D2D1D0GROUP BPORT C (LOWER)1 = INPUT0 = OUTPUTPORT B1 = INPUT0 = OUTPUTMODE SELECTION0 = MODE 01 = MODE 1GROUP APORT C (UPPER)1 = INPUT0 = OUTPUTPORT A1 = INPUT0 = OUTPUTMODE SELECTION00 = MODE 001 = MODE 11X = MODE 2MODE SET FLAG1 = ACTIVEFIGURE 2B.PORT B AND C BUS-HOLD CONFIGURATIONFIGURE 2.BUS-HOLD CONFIGURATIONOperational DescriptionMode SelectionTherearethreebasicmodesofoperationthancanbeselected by the system software:Mode 0 - Basic Input/OutputMode 1 - Strobed Input/OutputMode 2 - Bi-directional BusWhentheresetinputgoes“high”,allportswillbesettotheinputmodewithall24portlinesheldatalogic“one”levelbyinternalbusholddevices.Aftertheresetisremoved,the82C55Acanremainintheinputmodewithnoadditionalini-tializationrequired.Thiseliminatestheneedtopulluporpull-downresistorsinall-CMOSdesigns.ThecontrolwordFIGURE 4.MODE DEFINITION FORMAT4

82C55AThemodesforPortAandPortBcanbeseparatelydefined,whilePortCisdividedintotwoportionsasrequiredbythePortAandPortBdefinitions.Alloftheoutputregisters,includingthestatusflip-flops,willberesetwheneverthemodeischanged.Modesmaybecombinedsothattheirfunctionaldefinitioncanbe“tailored”toalmostanyI/Ostructure.Forinstance:GroupBcanbeprogrammedinMode0tomonitorsimpleswitchclosingsordisplaycompu-tationalresults,GroupAcouldbeprogrammedinMode1tomonitorakeyboardortapereaderonaninterrupt-drivenbasis.Themodedefinitionsandpossiblemodecombinationsmayseemconfusingatfirst,butafteracursoryreviewofthecompletedeviceoperationasimple,logicalI/Oapproachwillsurface.Thedesignofthe82C55AhastakenintoaccountthingssuchasefficientPCboardlayout,controlsignaldefi-nitionvs.PClayoutandcompletefunctionalflexibilitytosup-portalmostanyperipheraldevicewithnoexternallogic.Suchdesignrepresentsthemaximumuseoftheavailablepins.Single Bit Set/Reset Feature (Figure 5)AnyoftheeightbitsofPortCcanbeSetorResetusingasingleOutputinstruction.Thisfeaturereducessoftwarerequirements in control-based applications.WhenPortCisbeingusedasstatus/controlforPortAorB,thesebitscanbesetorresetbyusingtheBitSet/Resetoperation just as if they were output ports.CONTROL WORDD7D6D5D4D3D2D1D0XXDON’TCAREXBIT SET/RESET1 = SET0 = RESETBIT SELECT01234010100011000001ThisfunctionallowstheprogrammertoenableordisableaCPUinterruptbyaspecificI/Odevicewithoutaffectinganyother device in the interrupt structure.INTE Flip-Flop Definition(BIT-SET)-INTE is SET - Interrupt Enable(BIT-RESET)-INTE is Reset - Interrupt DisableNOTE:All Mask flip-flops are automatically reset during mode se-lection and device Reset.Operating ModesMode0(BasicInput/Output).Thisfunctionalconfigurationprovidessimpleinputandoutputoperationsforeachofthethreeports.Nohandshakingisrequired,dataissimplywrit-ten to or read from a specific port.Mode 0 Basic Functional Definitions:•Two 8-bit ports and two 4-bit ports•Any Port can be input or output•Outputs are latched•Input are not latched•16 different Input/Output configurations possibleMODE 0 PORT DEFINITIONAD40000D30000111100001111D10011001100110011BD00101010101010101GROUP APORTCPORTA(Upper)OutputOutputOutputOutputOutputOutputOutputOutputInputInputInputInputInputInputInputInputOutputOutputOutputOutputInputInputInputInputOutputOutputOutputOutputInputInputInputInput#01234567101112131415GROUP BPORTCPORTB(Lower)OutputOutputInputInputOutputOutputInputInputOutputOutputInputInputOutputOutputInputInputOutputInputOutputInputOutputInputOutputInputOutputInputOutputInputOutputInputOutputInput5101601171B01B11B2000011111111BIT SET/RESET FLAG0 = ACTIVEFIGURE 5.BIT SET/RESET FORMATInterrupt Control FunctionsWhenthe82C55Aisprogrammedtooperateinmode1ormode2,controlsignalsareprovidedthatcanbeusedasinterruptrequestinputstotheCPU.Theinterruptrequestsignals,generatedfromportC,canbeinhibitedorenabledbysettingorresettingtheassociatedINTEflip-flop,usingthebit set/reset function of port C.5

82C55AMode 0 (Basic Input)RDtIRINPUTtARCS, A1, A0tRAtRRtHRD7-D0tRDtDFMode 0 (Basic Output)WRtWWtWDtDWD7-D0tAWCS, A1, A0tWAOUTPUTtWBMode 0 ConfigurationsCONTROL WORD #0D7D6D5D4D3D2D1D010000000A82C55A84PA7 - PA082C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BCCONTROL WORD #2D7D6D5D4D3D2D1D010000010A84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BCONTROL WORD #1D7D6D5D4D3D2D1D010000001A82C55A84PA7 - PA0CONTROL WORD #3D7D6D5D4D3D2D1D010000011A82C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BC84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0B6

82C55AMode 0 Configurations (Continued)CONTROL WORD #4D7D6D5D4D3D2D1D010001000A82C55A84PA7 - PA082C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BCCONTROL WORD #8D7D6D5D4D3D2D1D010010000A84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BCONTROL WORD #5D7D6D5D4D3D2D1D010001001A82C55A84PA7 - PA0CONTROL WORD #9D7D6D5D4D3D2D1D010010001A82C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BC84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BCONTROL WORD #6D7D6D5D4D3D2D1D010001010A82C55A84PA7 - PA0CONTROL WORD #10D7D6D5D4D3D2D1D010010010A82C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BC84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BCONTROL WORD #7D7D6D5D4D3D2D1D010001011A82C55A84PA7 - PA0CONTROL WORD #11D7D6D5D4D3D2D1D010010011A82C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BC84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0B7

82C55AMode 0 Configurations (Continued)CONTROL WORD #12D7D6D5D4D3D2D1D010011000A82C55A84PA7 - PA082C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BCCONTROL WORD #14D7D6D5D4D3D2D1D010011010A84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BCONTROL WORD #13D7D6D5D4D3D2D1D010011001A82C55A84PA7 - PA0CONTROL WORD #15D7D6D5D4D3D2D1D010011011A82C55APC7 - PC4D7 - D0PC3 - PC0PB7 - PB0BC84PA7 - PA0PC7 - PC4D7 - D0C4848PC3 - PC0PB7 - PB0BOperating ModesMode1-(StrobedInput/Output).Thisfunctionalconfigura-tionprovidesameansfortransferringI/Odatatoorfromaspecifiedportinconjunctionwithstrobesor“handshaking”signals.Inmode1,portAandportBusethelinesonportCto generate or accept these “hand shaking” signals.Mode 1 Basic Function Definitions:•Two Groups (Group A and Group B)•Each group contains one 8-bit port and one 4-bitcontrol/data port•The 8-bit data port can be either input or output. Bothinputs and outputs are latched.•The 4-bit port is used for control and status of the 8-bitport.Input Control Signal Definition(Figures 6 and 7)STB (Strobe Input)A “low” on this input loads data into the input latch.RDCONTROL WORDD7D6D5D4D3D2D1D010111/0PC6, PC71 = INPUT0 = OUTPUTMODE 1 (PORT A)PA7-PA0INTEAPC4PC58STBAIBFAPC3RDPC6, PC72INTRAI/OMODE 1 (PORT B)CONTROL WORDD7D6D5D4D3D2D1D0111PB7-PB0INTEBPC2PC18STBBIBFBPC0INTRBIBF (Input Buffer Full F/F)A“high”onthisoutputindicatesthatthedatahasbeenloadedintotheinputlatch:inessence,andacknowledg-ment.IBFissetbySTBinputbeinglowandisresetbytherising edge of theRD input.FIGURE 6.MODE 1 INPUT8

82C55AtSTSTBtSIBIBFtSITINTRtRIBtRITRDtPHINPUT FROMPERIPHERALtPSFIGURE 7.MODE 1 (STROBED INPUT)INTR (Interrupt Request)A“high”onthisoutputcanbeusedtointerrupttheCPUwhenandinputdeviceisrequestingservice.INTRissetbythecondition:STBisa“one”,IBFisa“one”andINTEisa“one”.ItisresetbythefallingedgeofRD.ThisprocedureallowsaninputdevicetorequestservicefromtheCPUbysimply strobing its data into the port.INTE AControlled by bit set/reset of PC4.INTE BControlled by bit set/reset of PC2.Output Control Signal Definition(Figure 8 and 9)OBF - Output Buffer Full F/F). TheOBF output will go “low”toindicatethattheCPUhaswrittendataouttobespecifiedport.ThisdoesnotmeanvaliddataissentoutofthepartatthistimesinceOBFcangotruebeforedataisavailable.DataisguaranteedvalidattherisingedgeofOBF,(SeeNote1).TheOBFF/FwillbesetbytherisingedgeoftheWR input and reset byACK input being low.ACK-AcknowledgeInput).A“low”onthisinputinformsthe82C55AthatthedatafromPortAorPortBisreadytobeaccepted.Inessence,aresponsefromtheperipheraldeviceindicating that it is ready to accept data, (See Note 1).INTR-(InterruptRequest).A“high”onthisoutputcanbeusedtointerrupttheCPUwhenanoutputdevicehasaccepteddatatransmittedbytheCPU.INTRissetwhenACKisa“one”,OBFisa“one”andINTEisa“one”.Itisreset by the falling edge ofWR.INTE AControlled by Bit Set/Reset of PC6.INTE BControlled by Bit Set/Reset of PC2.NOTE:1.Tostrobedataintotheperipheraldevice,theusermustoperatethestrobelineinahandshakingmode.TheuserneedstosendOBFtotheperipheraldevice,generatesanACKfromthepe-ripheraldeviceandthenlatchdataintotheperipheraldeviceonthe rising edge ofOBF.MODE 1 (PORT A)CONTROL WORDD7D6D5D4D3D2D1D010111/0PC4, PC51 = INPUT0 = OUTPUTINTEAPA7-PA0PC7PC68OBFAACKAPC3WRPC4, PC52INTRAMODE 1 (PORT B)CONTROL WORDD7D6D5D4D3D2D1D0110INTEBPB7-PB0PC1PC28OBFBACKBPC0WRINTRBFIGURE 8.MODE 1 OUTPUT9

82C55AtWOBWRtAOBOBFINTRtWITACKtAKOUTPUTtWBtAITFIGURE 9.MODE 1 (STROBED OUTPUT)PA7-PA0RDCONTROL WORDD7D6D5D4D3D2D1D010111/010PC6, PC71 = INPUT0 = OUTPUTWRPC4PC5PC3PC6, PC7PB7, PB0PC1PC2PC08STBAIIBFAINTRA28OBFBACKBINTRBI/OWRCONTROL WORDD7D6D5D4D3D2D1D010101/011PC4, PC51 = INPUT0 = OUTPUTRDPA7-PA0PC7PC6PC3PC4, PC5PB7, PB0PC2PC1PC08OBFAACKAINTRA28STBBIBFBINTRBI/OPORT A - (STROBED INPUT)PORT B - (STROBED OUTPUT)PORT A - (STROBED OUTPUT)PORT B - (STROBED INPUT)CombinationsofMode1:PortAandPortBcanbeindividuallydefinedasinputoroutputinMode1tosupportawidevarietyofstrobedI/Oapplications.FIGURE 10.COMBINATIONS OF MODE 1Operating ModesMode 2 (Strobed Bi-Directional Bus I/O)Thefunctionalconfigurationprovidesameansforcommuni-catingwithaperipheraldeviceorstructureonasingle8-bitbusforbothtransmittingandreceivingdata(bi-directionalbusI/O).“Handshaking”signalsareprovidedtomaintainproperbusflowdisciplinesimilartoMode1.Interruptgener-ation and enable/disable functions are also available.Mode 2 Basic Functional Definitions:•Used in Group A only•One 8-bit, bi-directional bus Port (Port A) and a 5-bitcontrol Port (Port C)•Both inputs and outputs are latched•The 5-bit control port (Port C) is used for control andstatus for the 8-bit, bi-directional bus port (Port A)Bi-Directional Bus I/O Control Signal Definition(Figures 11, 12, 13, 14)Output OperationsOBF-(OutputBufferFull).TheOBFoutputwillgo“low”toindicate that the CPU has written data out to port A.ACK-(Acknowledge).A“low”onthisinputenablesthethree-stateoutputbufferofportAtosendoutthedata.Oth-erwise, the output buffer will be in the high impedance state.INTE1-(TheINTEflip-flopassociatedwithOBF).Con-trolled by bit set/reset of PC4.Input OperationsSTB-(StrobeInput).A“low”onthisinputloadsdataintotheinput latch.IBF-(InputBufferFullF/F).A“high”onthisoutputindicatesthat data has been loaded into the input latch.INTE2-(TheINTEflip-flopassociatedwithIBF).Controlledby bit set/reset of PC4.INTR-(InterruptRequest).AhighonthisoutputcanbeusedtointerrupttheCPUforbothinputoroutputoperations.10

82C55ACONTROL WORDD7D6D5D4D3D2D1D0111/01/01/0PC3PA7-PA0PC7PC2-PC01 = INPUT0 = OUTPUTPORT B1 = INPUT0 = OUTPUTGROUP B MODE0 = MODE 01 = MODE 1WR3INTE1PC68INTRAOBFAACKAINTE2PC4PC5STBAIBFARDPC2-PC0I/OFIGURE 11.MODE CONTROL WORDFIGURE 12.MODE 2DATA FROMCPU TO 82C55AWRtAOBOBFtWOBINTRtAKACKtSTSTBtSIBIBFtPSPERIPHERALBUStPHRDDATA FROMPERIPHERAL TO 82C55ADATA FROM82C55A TO PERIPHERALDATA FROM82C55A TO CPUtRIBtADtKDNOTE:Any sequence whereWR occurs beforeACK andSTB occurs before RD is permissible. (INTR = IBF• MASK•STB•RD÷OBF•MASK•ACK•WR)FIGURE 13.MODE 2 (BI-DIRECTIONAL)11

82C55AMODE 2 AND MODE 0 (INPUT)PC3PA7-PA0PC7CONTROL WORDD7D6D5D4D3D2D1D011011/0PC6PC4PC5PC2-PC0PB7-PB0WR38OBFAACKASTBAIBFAI/OCONTROL WORDD7D6D5D4D3D2D1D011001/0INTRAMODE 2 AND MODE 0 (OUTPUT)PC3PA7-PA0PC7PC6PC4PC5PC2-PC0PB7, PB0WR38OBFAACKASTBAIBFAI/OINTRAPC2-PC01 = INPUT0 = OUTPUTRDPC2-PC01 = INPUT0 = OUTPUTRD88MODE 2 AND MODE 1 (OUTPUT)PC3PA7-PA0PC7CONTROL WORDD7D6D5D4D3D2D1D01110PC6PC4PC5PB7-PB0PC1RDPC2PC08OBFBACKBINTRB8OBFAACKASTBAIBFAINTRAMODE 2 AND MODE 1 (INPUT)PC3PA7-PA0PC7CONTROL WORDD7D6D5D4D3D2D1D01111PC6PC4PC5PB7-PB0PC2RDPC1PC08STBBIBFBINTRB8OBFAACKASTBAIBFAINTRAWRWRFIGURE 14.MODE 2 COMBINATIONS12

82C55AMODE DEFINITION SUMMARYMODE 1OUTOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutINInInInInInInInInInInInInInInInInINTRBIBFBSTBBINTRASTBAIBFAI/OI/OOUTOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutOutINTRBOBFBACKBINTRAI/OI/OACKAOBFAI/OI/OI/OINTRASTBAIBFAACKAOBFAMODE 0INPA0PA1PA2PA3PA4PA5PA6PA7PB0PB1PB2PB3PB4PB5PB6PB7PC0PC1PC2PC3PC4PC5PC6PC7InInInInInInInInInInInInInInInInInInInInInInInInMODE 2GROUP A ONLYMode 0or Mode 1OnlySpecial Mode Combination ConsiderationsThereareseveralcombinationsofmodespossible.Foranycombination,someorallofPortClinesareusedforcontrolorstatus.Theremainingbitsareeitherinputsoroutputsasdefined by a “Set Mode” command.DuringareadofPortC,thestateofallthePortClines,excepttheACKandSTBlines,willbeplacedonthedatabus.InplaceoftheACKandSTBlinestates,flagstatuswillappearonthedatabusinthePC2,PC4,andPC6bitpositions as illustrated by Figure 17.Througha“WritePortC”command,onlythePortCpinsprogrammedasoutputsinaMode0groupcanbewritten.Nootherpinscanbeaffectedbya“WritePortC”command,norcantheinterruptenableflagsbeaccessed.TowritetoanyPortCoutputprogrammedasanoutputinMode1grouportochangeaninterruptenableflag,the“Set/ResetPortCBit” command must be used.Witha“Set/ResetPortCeaBit”command,anyPortClineprogrammedasanoutput(includingIBFandOBF)canbewritten,oraninterruptenableflagcanbeeithersetorreset.PortClinesprogrammedasinputs,includingACKandSTBlines,associatedwithPortCfarenotaffectedbya“Set/ResetPortCBit”command.Writingtothecorrespond-ingPortCbitpositionsoftheACKandSTBlineswiththe“SetResetPortCBit”commandwillaffecttheGroupAandGroup B interrupt enable flags, as illustrated in Figure 17.D7I/OD6I/OINPUT CONFIGURATIOND5IBFAD4D3D2D1IBFBD0INTRBINTEAINTRAINTEBGROUP AOUTPUT CONFIGURATIOND7D6D5I/OGROUP AD4I/OD3D2GROUP BD1D0OBFAINTEAINTRAINTEBOBFBINTRBGROUP BFIGURE 15.MODE 1 STATUS WORD FORMATD7D6D5IBFAD4D3D2XD1XGROUP BD0XOBFAINTE1INTE2INTRAGROUP A(Defined by Mode 0 or Mode 1 Selection)FIGURE 16.MODE 2 STATUS WORD FORMATCurrent Drive CapabilityAnyoutputonPortA,BorCcansinkorsource2.5mA.Thisfeatureallowsthe82C55AtodirectlydriveDarlingtontypedriversandhigh-voltagedisplaysthatrequiresuchsinkorsource current.13

82C55AReading Port C Status (Figures 15 and 16)InMode0,PortCtransfersdatatoorfromtheperipheraldevice.Whenthe82C55AisprogrammedtofunctioninModes1or2,PortCgeneratesoraccepts“handshaking”signalswiththeperipheraldevice.ReadingthecontentsofPortCallowstheprogrammertotestorverifythe“status”ofeachperipheraldeviceandchangetheprogramflowaccordingly.ThereisnotspecialinstructiontoreadthestatusinformationfromPortC.AnormalreadoperationofPortCisexecutedtoperform this function.INTERRUPTENABLE FLAGINTE BINTE A2INTE A1ALTERNATE PORT CPIN SIGNAL (MODE)ACKB (Output Mode 1)orSTBB (Input Mode 1)STBA (Input Mode 1 orMode 2)ACKA (Output Mode 1 orMode 2)Applications of the 82C55AThe82C55Aisaverypowerfultoolforinterfacingperipheralequipmenttothemicrocomputersystem.Itrepresentstheoptimumuseofavailablepinsandflexibleenoughtointer-facealmostanyI/Odevicewithouttheneedforadditionalexternal logic.Eachperipheraldeviceinamicrocomputersystemusuallyhasa“serviceroutine”associatedwithit.TheroutinemanagesthesoftwareinterfacebetweenthedeviceandtheCPU.Thefunctionaldefinitionofthe82C55AisprogrammedbytheI/Oserviceroutineandbecomesanextensionofthesystemsoftware.ByexaminingtheI/Odevicesinterfacecharacteristicsforbothdatatransferandtiming,andmatchingthisinformationtotheexamplesandtablesinthedetailedoperationaldescription,acontrolwordcaneasilybedevelopedtoinitializethe82C55Atoexactly“fit”theapplication.Figures18through24presentafewexamplesof typical applications of the 82C55A.POSITIONPC2PC4PC6FIGURE 17.INTERRUPT ENABLE FLAGS IN MODES 1 AND 2INTERRUPTREQUESTPA0PA1PA2PA3PA4PA5MODE 1PA6(OUTPUT)PA7PC7PC6PC5PC4DATA READYACKPAPER FEEDFORWARD/REV.PC3HIGH SPEEDPRINTERHAMMERRELAYS82C55APB0PB1PB2PB3PB4MODE 1PB5(OUTPUT)PB6PB7PC1PC2PC0INTERRUPTREQUESTCONTROL LOGICAND DRIVERSDATA READYACKPAPER FEEDFORWARD/REV.RIBBONCARRIAGE SEN.FIGURE 18.PRINTER INTERFACE14

82C55AINTERRUPTREQUESTPC3PA0PA1PA2PA3PA4PA5PA6PA7PC4PC5R0R1R2FULLYR3DECODEDR4KEYBOARDR5SHIFTCONTROLSTROBEACKMODE 1(INPUT)82C55APB0PB1PB2PB3PB4MODE 1PB5(OUTPUT)PB6PB7PC1PC2PC6PC7INTERRUPTREQUESTB0B1B2BURROUGHSSELF-SCANB3DISPLAYB4B5BACKSPACECLEARDATA READYACKBLANKINGCANCEL WORDINTERRUPTREQUESTPC3PA0PA1PA2PA3PA4PA5PA6PA7PC4PC5PC6PC7PB0PB1PB2PB3PB4PB5PB6PB7R0R1R2FULLYR3DECODEDR4KEYBOARDR5SHIFTCONTROLSTROBEACKBUST LTTEST LTTERMINALADDRESSMODE 1(INPUT)82C55AMODE 0(INPUT)FIGURE 19.KEYBOARD AND DISPLAY INTERFACEFIGURE20.KEYBOARDANDTERMINALADDRESSINTERFACEINTERRUPTREQUESTPA0PA1PA2PA3PA4MODE 0PA5(OUTPUT)PA6PA7PC4PC5PC6PC782C55APC0PC1BITSET/RESETPC2PC3PB0PB1PB2MODE 0(INPUT)PB3PC4PC5PC6PC7LSBPA0PA1PA2PA3PA4PA5MODE 1PA6(OUTPUT)PA7PC7PC6PC5PC4PC3R0R1R2CRT CONTROLLERR3• CHARACTER GEN.•REFRESH BUFFERR4•CURSOR CONTROLR5SHIFTCONTROLDATA READYACKBLANKEDBLACK/WHITE12-BITA/DCONVERTER(DAC)ANALOGOUTPUTSTB DATA82C55ASAMPLE ENSTBLSB8-BITD/ACONVERTER(ADC)ANALOGINPUTPC2PC1PC0PB0MODE 0PB1(OUTPUT)PB2PB3PB4PB5PB6PB7ROW STBCOLUMN STBCURSOR H/V STBCURSOR/ROW/COLUMNADDRESSH&VMABFIGURE 21.DIGITAL TO ANALOG, ANALOG TO DIGITALFIGURE 22.BASIC CRT CONTROLLER INTERFACE15

82C55AINTERRUPTREQUESTPC3PA0PA1PA2PA3PA4PA5PA6PA7PC4PC5PC7PC6PC2PC1PC0D0D1D2D3D4D5D6D7INTERRUPTREQUESTPC3PA0PA1PA2PA3PA4PA5PA6PA7PC4PC5PC682C55ATRACK “0” SENSORSYNC READYINDEXMODE 0(INPUT)PC0PC1PC2R0R1R2R3R4R5R6R7FLOPPY DISKCONTROLLERAND DRIVEMODE 1(INPUT)B LEVELPAPERTAPEREADERMODE 2DATA STBACK (IN)DATA READYACK (OUT)STBACKSTOP/GOMACHINE TOOLSTART/STOPLIMIT SENSOR (H/V)OUT OF FLUID82C55APB0PB1PB2MODE 0PB3(OUTPUT)PB4PB5PB6PB7ENGAGE HEADFORWARD/REV.READ ENABLEWRITE ENABLEDISC SELECTENABLE CRCTESTBUSY LTPB0PB1PB2MODE 0PB3(OUTPUT)PB4PB5PB6PB7CHANGE TOOLLEFT/RIGHTUP/DOWNHOR. STEP STROBEVERT. STEP STROBESLEW/STEPFLUID ENABLEEMERGENCY STOPFIGURE 23.BASIC FLOPPY DISC INTERFACEFIGURE 24.MACHINE TOOL CONTROLLER INTERFACE16

82C55AAbsolute Maximum RatingsTA = 25oCThermal InformationThermal Resistance (Typical, Note 1)θJAθJCoCERDIP Package . . . . . . . . . . . . . . . .50C/W10oC/WCLCC Package . . . . . . . . . . . . . . . . . .65oC/W14oC/WPDIP Package. . . . . . . . . . . . . . . . . . .50oC/WN/APLCC Package . . . . . . . . . . . . . . . . . .46oC/WN/AoMaximum Storage Temperature Range . . . . . . . . . .-65C to 150oCMaximum Junction TemperatureCDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oCPDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oCMaximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC(PLCC Lead Tips Only)Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0VInput, Output or I/O Voltage . . . . . . . . . . . .GND-0.5V to VCC+0.5VESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1Operating ConditionsVoltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to 5.5VOperating Temperature RangeC82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oCI82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to 85oCM82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oCDie CharacteristicsGate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 GatesCAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE:1.θJA is measured with the component mounted on an evaluation PC board in free air.Electrical SpecificationsVCC = 5.0V±10%; TA = 0oC to +70oC (C82C55A);TA = -40oC to +85oC (I82C55A);TA = -55oC to +125oC (M82C55A)LIMITSSYMBOLVIHVILVOHVOLIIIOIBHHIBHLIDARICCSBICCOPNOTES:PARAMETERLogical One Input VoltageLogical Zero Input VoltageLogical One Output VoltageLogical Zero Output VoltageInput Leakage CurrentI/O Pin Leakage CurrentBus Hold High CurrentBus Hold Low CurrentDarlington Drive CurrentStandby Power Supply CurrentOperating Power Supply CurrentMIN2.02.2-3.0VCC -0.4--1.0-10-5050-2.5--MAX-0.8-0.4+1.0+10-400400Note 2, 4101UNITSVVVVµAµAµAµAmAµAmA/MHzIOH = -2.5mA,IOH = -100µAIOL +2.5mATEST CONDITIONSI82C55A, C82C55A,M82C55AVIN = VCC or GND,DIP Pins: 5, 6, 8, 9, 35, 36VO = VCC or GND DIP Pins: 27 - 34VO = 3.0V. Ports A, B, CVO = 1.0V. Port A ONLYPorts A, B, C. Test Condition 3VCC = 5.5V, VIN = VCC or GND. Output OpenTA = +25oC, VCC = 5.0V, Typical (See Note 3)2.No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.3.ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA).4.Tested as VOH at -2.5mA.CapacitanceSYMBOLCINCI/OTA = 25oCPARAMETERTYPICAL1020UNITSpFpFTEST CONDITIONSFREQ = 1MHz, All Measurements arereferenced to device GNDInput CapacitanceI/O Capacitance17

82C55AAC Electrical SpecificationsVCC = +5V± 10%, GND = 0V; TA = -55oC to +125oC (M82C55A) (M82C55A-5);TA = -40oC to +85oC (I82C55A) (I82C55A-5);TA = 0oC to +70oC (C82C55A) (C82C55A-5)82C55A-5SYMBOLREAD TIMING(1) tAR(2) tRA(3) tRR(4) tRD(5) tDF(6) tRVWRITE TIMING(7) tAW(8) tWA(9) tWW(10) tDW(11) tWDOTHER TIMING(12) tWB(13) tIR(14) tHR(15) tAK(16) tST(17) tPS(18) tPH(19) tAD(20) tKD(21) tWOB(22) tAOB(23) tSIB(24) tRIB(25) tRIT(26) tSIT(27) tAIT(28) tWIT(29) tRESWR = 1 to OutputPeripheral Data BeforeRDPeripheral Data AfterRDACK Pulse WidthSTB Pulse WidthPeripheral Data Before STB HighPeripheral Data After STB HighACK = 0 to OutputACK = 1 to Output FloatWR = 1 to OBF = 0ACK = 0 to OBF = 1STB = 0 to IBF = 1RD = 1 to IBF = 0RD = 0 to INTR = 0STB = 1 to INTR = 1ACK = 1 to INTR = 1WR = 0 to INTR = 0Reset Pulse Width-002001002050-20--------500350------175250150150150150200150150200--002001002050-20--------500350------175250150150150150200150150200-nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns12111111111, (Note)1Address Stable BeforeWRAddress Stable AfterWRWR Pulse WidthData Valid toWR HighData Valid AfterWR High02010010030-----02010010030-----nsnsnsnsnsAddress Stable BeforeRDAddress Stable AfterRDRD Pulse WidthData Valid FromRDData Float AfterRDTime BetweenRDs and/orWRs00250-10300---20075-00150-10300---12075-nsnsnsnsnsns12PARAMETERMINMAX82C55AMINMAXUNITSTESTCONDITIONSNOTE:Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum.18

82C55ATiming WaveformsRDtIR (13)INPUTtAR (1)CS, A1, A0tRA (2)tRR (3)tHR (14)D7-D0tRD (4)tDF (5)FIGURE 25.MODE 0 (BASIC INPUT)WRtWW (9)tWD (11)tDW(10)D7-D0tAW (7)CS, A1, A0tWA (8)OUTPUTtWS (12)FIGURE 26.MODE 0 (BASIC OUTPUT)tST (16)STBtSIB(23)IBFtSIT(26)tRIT(25)tRIB (24)INTRRDtPH(18)INPUT FROMPERIPHERALtPS (17)FIGURE 27.MODE 1 (STROBED INPUT)19

82C55ATiming Waveforms (Continued)tWOB (21)WRtAOB (22)OBFINTRtWIT(28)ACKtAK (15)OUTPUTtWB (12)tAIT (27)FIGURE 28.MODE 1 (STROBED OUTPUT)DATA FROMCPU TO 82C55AWR(NOTE)tAOB(22)tWOB(21)INTRtAK(15)ACKtST(16)STB(NOTE)IBFtSIB(23)tAD (19)tPS (17)PERIPHERALBUStPH (18)RDDATA FROMPERIPHERAL TO 82C55ADATA FROM82C55A TO PERIPHERALDATA FROM82C55A TO CPUtRIB (24)tKD(20)OBFFIGURE 29.MODE 2 (BI-DIRECTIONAL)NOTE:Any sequence whereWR occurs beforeACK andSTB occurs beforeRD is permissible. (INTR = IBF•MASK•STB•RD•OBF•MASK•ACK•WR)20

82C55ATiming Waveforms (Continued)A0-A1,CStAW (7)DATABUStDW (10)WRtWD (11)DATABUStWW (9)tWA (8)RD(4) tRDVALIDHIGH IMPEDANCEA0-A1,CStAR (1)tRR (3)tDF (5)tRA (2)FIGURE 30.WRITE TIMINGFIGURE 31.READ TIMINGAC Test CircuitV1R1OUTPUT FROMDEVICE UNDERTESTTESTPOINTR2C1(SEE NOTE)AC Testing Input, Output WaveformsINPUTVIH + 0.4V1.5VVIL - 0.4V1.5VVOLOUTPUTVOHAC Testing:All AC Parameters tested as per test circuits. Input RISE andFALL times are driven at 1ns/V.TEST CONDITION DEFINITION TABLENOTE: Includes STRAY and JIG CapacitanceTEST CONDITION123V11.7VVCC1.5VR1523Ω2kΩ750ΩR2Open1.7kΩOpenC1150pF50pF50pFBurn-In CircuitsMD82C55A CERDIPF3F4F6F7F8F9F4F3GNDF0F1F10F6F7F8F9F10F6F7F8F9F10123456710111213141516171819204039383736353433323130292827262524232221F13F14F15F11F10F12F11F15F14VCCF12F13F7F8F9C1F11F12F13F14F2F5F15F11F12F13F14F15F11F12VCCC1GNDF0F1F10F6F7F8F9F10F671011121314151617181920212223242526272865432144434241403938373635343332313029MR82C55A CLCCF11F12F13F14F9F8F7F6F2F5F15F11F12F13F14F15F11F12NOTES:1.VCC = 5.5V± 0.5V2.VIH = 4.5V± 10%3.VIL = -0.2V to 0.4V4.GND = 0VNOTES:1.C1 = 0.01µF minimum2.All resistors are 47kΩ± 5%3.f0 = 100kHz± 10%4.f1 = f0÷ 2; f2 = f1÷ 2; . . . ; f15 = f14÷ 221

82C55ADie CharacteristicsDIE DIMENSIONS:95 x 100 x 19 ±1milsMETALLIZATION:

Type: Silicon - AluminumThickness: 11kű1kÅ

GLASSIVATION:Type: SiO2

Thickness: 8kű1kÅ

WORST CASE CURRENT DENSITY:0.78 x 105 A/cm2

Metallization Mask Layout82C55A

RDPA0PA1PA2PA3PA4PA5PA6PA7WRCSGNDA1A0PC7PC6PC5PC4PC0PC1

RESETD0D1D2D3D4D5D6D7VCC

PC2PD3PB0PB1PB2PB3PB4PB5PB6PB7

22

82C55ADual-In-Line Plastic Packages (PDIP)NINDEXAREAE1123N/2E40.6(JEDEC MS-011-AC ISSUE B)40 LEAD DUAL-IN-LINE PLASTIC PACKAGEINCHESSYMBOL-B-MILLIMETERSMIN-0.393.180.3560.770.20450.30.1315.2412.32MAX6.35-4.950.5581.770.38153.2-15.8714.73NOTES44--8-5565-6749Rev. 0 12/93MIN-0.0150.1250.0140.0300.0081.9800.0050.6000.485MAX0.250-0.1950.0220.0700.0152.095-0.6250.580AE-A-DBASEPLANESEATINGPLANED1B1B0.010 (0.25)MD1-C-A2LA1ACLA1A2BB1CDD1EE1eeAeBLNeAeCCeCABSeBNOTES:1.ControllingDimensions:INCH.IncaseofconflictbetweenEnglishand Metric dimensions, the inch dimensions control.2.Dimensioning and tolerancing per ANSI Y14.5M-1982.3.Symbolsaredefinedinthe“MOSeriesSymbolList”inSection2.2of Publication No. 95.4.DimensionsA,A1andLaremeasuredwiththepackageseatedinJEDEC seating plane gauge GS-3.5.D,D1,andE1dimensionsdonotincludemoldflashorprotrusions.Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).6.E andeAare measured with the leads constrained to be per-pendicular to datum-C-.7.eB and eC are measured at the lead tips with the leads uncon-strained. eC must be zero or greater.8.B1maximumdimensionsdonotincludedambarprotrusions.Dambar protrusions shall not exceed 0.010 inch (0.25mm).9.N is the maximum number of terminal positions.10.Cornerleads(1,N,N/2andN/2+1)forE8.3,E16.3,E18.3,E28.3,E42.6willhaveaB1dimensionof0.030-0.045inch(0.76-1.14mm).0.100 BSC0.600 BSC-0.115400.7000.200-2.54 BSC15.24 BSC17.785.08402.9323

82C55APlastic Leaded Chip Carrier Packages (PLCC)0.042 (1.07)0.048 (1.22)PIN (1) IDENTIFIERCL0.042 (1.07)0.056 (1.42)0.050 (1.27) TPN44.65(JEDEC MS-018AC ISSUE A)0.004 (0.10)C44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGESYM-BOLAA1INCHESMIN0.1650.0900.6850.6500.2910.6850.6500.29144MAX0.1800.1200.6950.6560.3190.6950.6560.319MILLIMETERSMIN4.202.2917.4016.517.4017.4016.517.4044MAX4.573.0417.6516.668.1017.6516.668.10NOTES---34, 5-34, 56Rev. 211/970.025 (0.)R0.045 (1.14)D2/E2CLD2/E2VIEW “A”DD1D2EE1E2NE1ED1D0.020 (0.51) MAX3 PLCSA1A0.020 (0.51)MINSEATING-C-PLANE0.026 (0.66)0.032 (0.81)0.013 (0.33)0.021 (0.53)0.045 (1.14)MIN0.025 (0.)MINVIEW “A” TYP.NOTES:1.Controllingdimension:INCH.Convertedmillimeterdimensionsare not necessarily exact.2.Dimensions and tolerancing per ANSI Y14.5M-1982.3.Dimensions D1 and E1 do not include mold protrusions. Allow-ablemoldprotrusionis0.010inch(0.25mm)perside.Dimen-sionsD1andE1includemoldmismatchandaremeasuredatthe extreme material condition at the body parting line.4.To be measured at seating plane-C- contact point.5.Centerlinetobedeterminedwherecenterleadsexitplasticbody.6.“N” is the number of terminal positions.24

82C55ACeramic Dual-In-Line Frit Seal Packages (CERDIP)c1-A--D-BASEMETALEb1M-B-bbbSBASEPLANESEATINGPLANES1b2bcccMCA - BSAACA - BSDQ-C-ALDSM(b)SECTION A-A(c)LEAD FINISHF40.6MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGEINCHESSYMBOLAbb1b2b3cc1MIN-0.0140.0140.0450.0230.0080.008-0.510MAX0.2250.0260.0230.0650.0450.0180.0152.0960.620MILLIMETERSMIN-0.360.361.140.580.200.20-12.95MAX5.720.660.581.651.140.460.3853.2415.752.54 BSC15.24 BSC7.62 BSC3.180.380.1390o----405.081.78-105o0.380.760.250.038NOTES-23-42355----67----2, 38Rev. 0 4/94αeADEeeAeA/2LQS1eDSeA/2c0.100 BSC0.600 BSC0.300 BSC0.1250.0150.00590o----400.2000.070-105o0.0150.0300.0100.0015aaaMCA - BSDSNOTES:1.Indexarea:Anotchorapinoneidentificationmarkshallbelocat-edadjacenttopinoneandshallbelocatedwithintheshadedareashown.Themanufacturer’sidentificationshallnotbeusedas a pin one identification mark.2.ThemaximumlimitsofleaddimensionsbandcorMshallbemeasuredatthecentroidofthefinishedleadsurfaces,whensolder dip or tin plate lead finish is applied.3.Dimensionsb1andc1applytoleadbasemetalonly.DimensionM applies to lead plating and finish thickness.4.Cornerleads(1,N,N/2,andN/2+1)maybeconfiguredwithapartialleadpaddle.Forthisconfigurationdimensionb3replacesdimension b2.5.Thisdimensionallowsforoff-centerlid,meniscus,andglassoverrun.6.DimensionQshallbemeasuredfromtheseatingplanetothebase plane.7.Measure dimension S1 at all four corners.8.N is the maximum number of terminal positions.9.Dimensioning and tolerancing per ANSI Y14.5M - 1982.10.Controlling dimension: INCH.αaaabbbcccMN25

82C55ACeramic Leadless Chip Carrier Packages (CLCC)0.010SEHSDD3J44.AMIL-STD-1835 CQCC1-N44 (C-5)44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGEINCHESSYMBOLAA1BB1B2B3DD1D2MIN0.00.0540.0330.0220.0060.0MAX0.1200.0880.0390.0280.0220.662MILLIMETERSMIN1.631.370.840.560.1516.26MAX3.052.240.990.710.5616.81NOTES6, 7-42, 4-----2---2--255----333Rev. 0 5/18/94j x 45oBE3E0.072 REF1.83 REF0.500 BSC0.250 BSC-0.00.6620.66212.70 BSC6.35 BSC-16.2616.8116.81h x 45o0.010SEFSAA1PLANE 2PLANE 1D3EE1E2E3ee1hj0.007MEFSHSB10.500 BSC0.250 BSC-0.0150.662-12.70 BSC6.35 BSC-0.381.02 REF0.51 REF1.141.141.900.081111441.401.402.410.3816.811.27 BSC0.050 BSC0.040 REF0.020 REF0.0450.0450.0750.0031111440.0550.0550.0950.015-E-LL1L3eL-H-L2L3NDNEN-F-E1B3NOTES:1.Metallizedcastellationsshallbeconnectedtoplane1terminalsandextendtowardplane2acrossatleasttwolayersofceramicorcompletelyacrossalloftheceramiclayerstomakeelectricalconnection with the optional plane 2 terminals.2.Unlessotherwisespecified,aminimumclearanceof0.015inch(0.38mm)shallbemaintainedbetweenallmetallizedfeatures(e.g., lid, castellations, terminals, thermal pads, etc.)3.Symbol“N”isthemaximumnumberofterminals.Symbols“ND”and“NE”arethenumberofterminalsalongthesidesoflength“D” and “E”, respectively.4.Therequiredplane1terminalsandoptionalplane2terminals(ifused) shall be electrically connected.5.Thecornershape(square,notch,radius,etc.)mayvaryatthemanufacturer’s option, from that shown on the drawing.6.Chipcarriersshallbeconstructedofaminimumoftwoceramiclayers.7.Dimension “A” controls the overall package thickness. The maxi-mum“A”dimensionispackageheightbeforebeingsolderdipped.8.Dimensioning and tolerancing per ANSI Y14.5M-1982.9.Controlling dimension:INCH.E2L2B2L1e1D1D226