巴克码发生器“01110010”
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity bak1 is
port( clk,reset: in std_logic;
dout:out std_logic);
end bak1;
architecture a of bak1 is
signal count :std_logic_vector(2 downto 0);
signal tmp1:std_logic;
begin
dout<=tmp1;
process(clk,reset)
begin
if reset='0' then
count<=(others=>'0');
elsif rising_edge(clk) then
count<=count+1;
case count is
when \"000\"=>tmp1<='0' ;
when \"001\"=>tmp1<='1' ;
when \"010\"=>tmp1<='1' ;
when \"011\"=>tmp1<='1' ;
when \"100\"=>tmp1<='0' ;
when \"101\"=>tmp1<='0' ;
when \"110\"=>tmp1<='1' ;
when \"111\"=>tmp1<='0' ;
when others=>tmp1<='0';
end case;
end if;
end process;
end a;
巴克码检测器“01110010”
library ieee;
use ieee.std_logic_11.all;
entity JianMaQi is
port(data,clk,reset:in std_logic;
dout:out std_logic);
end;
architecture a of JianMaQi is
signal q0,q1,q2,q3,q4,q5,q6,q7: std_logic;
begin
process(clk,data,reset)
begin
if(clk'event and clk='1') then
q0<=data;
q1<=q0;
q2<=q1;
q3<=q2;
q4<=q3;
q5<=q4;
q6<=q5;
q7<=q6;
end if;
end process;
process(clk)
variable q:std_logic;
begin
q:=(not q7)and q6 and q5 and q4 and (not q3) and (not q2) and q1 and (not q0);
dout<=q and reset;
end process;
end;
