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专利名称：SMART VERIFY FOR MULTI-STATE
MEMORIES
发明人：GONGWER, Geoffrey, S.,GUTERMAN, Daniel,
C.,FONG, Yupin, Kawing
申请号：EP03787219.9申请日：20031201公开号：EP1568041B1公开日：20070321
摘要：The present invention presents a 'smart verify' technique whereby multi-statememories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique canincrease multi-state write speed while maintaining reliable operation within sequentiallyverified, multi-state memory implementations. It does so by providing 'intelligent' meansto minimize the number of sequential verify operations for each program/verify/lockoutstep of the write sequence. In an exemplary embodiment of the write sequence for themulti-state memory during a program/verify cycle sequence of the selected storageelements, at the beginning of the process only the lowest state of the multi-state rangeto which the selected storage elements are being programmed is checked during theverify phase. Once the first storage state is reached by one or more of the selectedelements, the next state in the sequence of multi-states is added to the verify process.This next state can either be added immediately upon the fastest elements reaching thispreceding state in the sequence or after a delay of several program cycles. The adding ofstates to the set being checked in the verify phase continues through the rest of the set
of multi-states in sequence, until the highest state has been added. Additionally, lowerstates can be removed from the verify set as all of the selected storage elements boundfor these levels verify successfully to those target values and are locked out fromfurther programming.
申请人：SANDISK CORP
地址：US
国籍：US
代理机构：Hitchcock, Esmond Antony
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