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专利名称：APPARATUS AND METHOD FOR
MULTIPLYING, SUMMING, AND
ACCUMULATING SETS OF PACKED BYTES
发明人：VENKATESWARA MADDURI,ELMOUSTAPHA
OULD-AHMED-VALL,ROBERT
VALENTINE,MARK CHARNEY,JESUS CORBAL
申请号：US15850499申请日：20171221
公开号：US20190196813A1公开日：20190627
专利附图：
摘要：An apparatus and method for performing multiplication, summation, negation,sign extension, and accumulation with packed bytes. For example, one embodiment of aprocessor comprises: a decoder to decode an instruction to generate a decodedinstruction, the instruction including an opcode, and a plurality of operands identifying aplurality of packed data source registers and a packed data destination register; a firstsource register to store a first plurality of packed signed bytes; a second source registerto store a second plurality of packed signed bytes; execution circuitry to execute thedecoded instruction, the execution circuitry comprising: multiplier circuitry to multiplyeach packed signed byte from the first source register with a corresponding packedsigned byte from the second source register to generate a plurality of temporaryproducts, adder circuitry to add a plurality of sets of the temporary products togenerate a plurality of temporary sums; negation and extension circuitry to negate andextend each of the temporary sums to doublewords sums; and accumulation circuitry toadd each of the doublewords sums to a doubleword from a third source register togeneral final doubleword results; and a packed data destination register to store thefinal doubleword results in specified data element locations.
申请人：Intel Corporation
地址：Santa Clara CA US
国籍：US
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